Kurs/Prototyping med FPGA: Difference between revisions
< Kurs
(laget siden) |
No edit summary |
||
| Line 3: | Line 3: | ||
<b>Kursholder</b>: Odd Rune S. Lykkebø | <b>Kursholder</b>: Odd Rune S. Lykkebø | ||
( | The course will take a stab at explaining the common basics of commercial FPGAs. We will then demonstrate the basics of hardware design languages (HDL) and present an example of prototyping a design in FPGA where we go slightly in-depth about the tools used and the results they produce. We will also touch briefly on the subject of achieving timing closure in high-speed designs. | ||
Revision as of 10:03, 19 October 2010
Tid: Torsdag 4. november 2010, kl. 18:15
Sted: Annonseres senere
Kursholder: Odd Rune S. Lykkebø
The course will take a stab at explaining the common basics of commercial FPGAs. We will then demonstrate the basics of hardware design languages (HDL) and present an example of prototyping a design in FPGA where we go slightly in-depth about the tools used and the results they produce. We will also touch briefly on the subject of achieving timing closure in high-speed designs.