Kurs/Prototyping med FPGA: Difference between revisions
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<b>Tid</b>: Torsdag 4. november 2010, kl. 18:15<BR> | <b>Tid</b>: Torsdag 4. november 2010, kl. 18:15<BR> | ||
<b>Sted</b>: | <b>Sted</b>: [[../Hvor er R9?|R9]]<BR> | ||
<b>Kursholder</b>: Odd Rune S. Lykkebø | <b>Kursholder</b>: Odd Rune S. Lykkebø | ||
The course will take a stab at explaining the common basics of commercial FPGAs. We will then demonstrate the basics of hardware design languages (HDL) and present an example of prototyping a design in FPGA where we go slightly in-depth about the tools used and the results they produce. We will also touch briefly on the subject of achieving timing closure in high-speed designs. | The course will take a stab at explaining the common basics of commercial FPGAs. We will then demonstrate the basics of hardware design languages (HDL) and present an example of prototyping a design in FPGA where we go slightly in-depth about the tools used and the results they produce. We will also touch briefly on the subject of achieving timing closure in high-speed designs. | ||
The course is aimed at people interested in hardware. | |||
The prerequisites are: | |||
- Some knowledge on basic electrical engineering; if you can piece together how a ripple-carry adder works, you're within scope. | |||
Latest revision as of 12:10, 29 October 2010
Tid: Torsdag 4. november 2010, kl. 18:15
Sted: R9
Kursholder: Odd Rune S. Lykkebø
The course will take a stab at explaining the common basics of commercial FPGAs. We will then demonstrate the basics of hardware design languages (HDL) and present an example of prototyping a design in FPGA where we go slightly in-depth about the tools used and the results they produce. We will also touch briefly on the subject of achieving timing closure in high-speed designs.
The course is aimed at people interested in hardware.
The prerequisites are:
- Some knowledge on basic electrical engineering; if you can piece together how a ripple-carry adder works, you're within scope.